Algo-Logic Systems has internally developed a variety of pre-built Intellectual Property (IP) cores. The IP cores comprise Algo-Logic's FPGA accelerated Gateware Defined Networking® (GDN) solutions that achieve high throughput with minimal power and sub-microsecond latency. GDN solutions reduce total cost of ownership (TCO) and time-to-market within the Accelerated Finance, Data Center, and Internet of Things industries.
- Configurable cores support multiple tables, varied key-sizes, and differing entries per table.
- Capability to enhance features in the cores.
- The lowest latency possible is achieved by parsing in FPGA hardware.
- Ability to customize a solution by combining our different soft cores into a single device.
- Minimal development time.
- Integrates with other standard System on Chip (SoC) designs.
- Graphical User Interface (GUI) and RESTful APIs are provided for control and monitoring.
Performs lookups required to manage flows, as needed for Software Defined Networks (SDN) and Voice over IP (VoIP).
Implements a full TCP endpoint in FPGA hardware which is capable of opening, maintaining, and closing TCP Connections; has an ultra low latency of 76-nanoseconds.
Implements a full TCP functionality in FPGA hardware that is capable of opening, maintaining, and closing TCP Connections; has a receive-side ultra-low-latency of 96-nanoseconds.
Our ULL PHY+MAC design implements 10GBASE-R MAC and PCS (Physical Coding Sub-layer) functionality in an FPGA by using logic optimized for latency.
Rapidly transfers data between Field Programmable Gate Array (FPGA) logic, processors, and memory.