Algo-Logic builds accelerated trading solutions that have the lowest delay and time variation bounds possible. We have a rich library of pre-built infrastructure that helps minimize time to market. By implementing order processing algorithms in FPGA hardware, sub-microsecond (µs) processing delays with only nanoseconds (ns) of time variation is achieved, which is impossible to obtain in software. Algo-Logic offers finance protocol parsing libraries with support for FIX, OUCH, XPRS, ArcaDirect, BOE, and LSE.
- The lowest latency possible is achieved by parsing in FPGA hardware.
- Deterministic performance eliminates order processing time variations.
- UDP/IP-based control and monitoring interface makes operation of the hardware easy from graphical and command line interfaces.
- TCP/IP-based order processing implemented directly in FPGA hardware.
- Line rate processing at 10 Gigabits/second.
Reads market data and execution reports directly from 10Gbps SFP+ links then optionally generates and verifies order messages in the FPGA hardware and sends immediately back to the market.
Receives orders from market participants and disseminates market data to subscribers. Within the T2T system, the order sequencer module assigns a timestamp to orders and forwards the orders to the matching engines.
Consists of infrastructure components and protocol parsers that integrate to implement algorithmic trading solutions with the shortest possible time to market.