Ultra Low Latency Networking with FPGAs

With reference designs for trading on the Intel PAC D5005, learn how to trade with sub-microsecond latency using Field Programmable Gate Arrays with algorithms in logic. Algo-Logic's Gateware Defined Networking cores provide an Ultra-Low-Latency (ULL) MAC and TCP/IP networking stack on a Stratix 10 FPGA. Reference designs can be used to perform Pre-Trade Risk Checks (PTRCs) and Tick-to-Trade (T2T) with sub-microsecond latency.

Presented at the Intel FPGA Technology Day (IFTD) on Nov 18, 2020